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== Tiles that accept signal input == | == Tiles that accept signal input == | ||
A value of ''pulse'' in the ''toggle type'' column indicates that the tile only needs one [[frame]] of signal to toggle (i.e. only changes state when signal changes from OFF to ON), while ''steady'' indicates that the tile will be toggled only when the signal is active (i.e. changes state on both off-to-on and on-to-off transitions). | |||
A value of ''pulse'' in the ''toggle type'' column indicates that the tile only needs one frame of signal to toggle (i.e. only changes state when signal changes from OFF to ON), while ''steady'' indicates that the tile will be toggled only when the signal is active (i.e. changes state on both off-to-on and on-to-off transitions). | |||
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{{clear}} | {{clear}} | ||
== Gates == | == Gates == | ||
Gates are tiles that use existing signals to create new signals. They otherwise [[acting floor|behave like floor]], except that [[ice block]]s cannot melt on them, even though they cannot be destroyed by [[time bomb]]s (and therefore cannot be replaced by [[fire]] if a monster is on it). The lightning bolt has no effect on these tiles. | Gates are tiles that use existing signals to create new signals. They otherwise [[acting floor|behave like floor]], except that [[ice block]]s cannot melt on them, even though they cannot be destroyed by [[time bomb]]s (and therefore cannot be replaced by [[fire]] if a monster is on it). The lightning bolt has no effect on these tiles. | ||
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[[File:NANDgate.png|left]] | [[File:NANDgate.png|left]] | ||
The '''NAND gate''' accepts two inputs. It is generally equivalent to an AND gate immediately followed by an inverter. If both input signals are ON, the output signal will be OFF. Otherwise, the output signal will be ON. | The '''NAND gate''' accepts two inputs. It is generally equivalent to an AND gate immediately followed by an inverter. If both input signals are ON, the output signal will be OFF. Otherwise, the output signal will be ON. | ||
The point of including a NAND gate when an inverter can simply be placed after a regular AND gate, aside from speed and compactness, may be to demonstrate [http://en.wikipedia.org/wiki/NAND_logic NAND logic]: all other logic gates can be constructed with only combinations of NAND gates. Its inclusion over a NOR gate would be arbitrary, as similar [http://en.wikipedia.org/wiki/NOR_logic NOR logic] exists. | |||
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=== Other gates === | === Other gates === | ||
==== Counter ==== | ==== Counter ==== | ||
{{Infobox Tile | {{Infobox Tile | ||
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|colspan=3|'''INPUT''' || '''OUTPUT''' | |colspan=3|'''INPUT''' || '''OUTPUT''' | ||
|- style="background:#def; text-align:center;" | |- style="background:#def; text-align:center;" | ||
| Latch || Data || Output (previous frame) || Output (current frame) | | Latch || Data || Output (previous [[frame]]) || Output (current frame) | ||
|- style="background:#dfd; text-align:center;" | |- style="background:#dfd; text-align:center;" | ||
|0 || 0 || 0 || 0 | |0 || 0 || 0 || 0 | ||
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=== Timing and loops === | === Timing and loops === | ||
At the start of a level, all inputs and outputs are OFF. On every frame after the first, all gates produce output based on their inputs from the ''previous'' frame. Because of this, each gate is considered to have a 1-frame "delay". For example, an AND gate followed by a NOT gate have a combined 2-frame delay, whereas a NAND gate only has a 1-frame delay, and therefore is not exactly equivalent even though the logic is the same. As another example, a chain of OR gates of length N will have an N-frame delay. This can be used to precisely control the timing and activation of various objects and parts of circuits. | At the start of a level, all inputs and outputs are OFF. On every frame after the first, all gates produce output based on their inputs from the ''previous'' frame. Because of this, each gate is considered to have a 1-frame "delay". For example, an AND gate followed by a NOT gate have a combined 2-frame delay, whereas a NAND gate only has a 1-frame delay, and therefore is not exactly equivalent even though the logic is the same. As another example, a chain of OR gates of length N will have an N-frame delay. This can be used to precisely control the timing and activation of various objects and parts of circuits. | ||