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[[File:NANDgate.png|left]] | [[File:NANDgate.png|left]] | ||
The '''NAND gate''' accepts two inputs. It is generally equivalent to an AND gate immediately followed by an inverter. If both input signals are ON, the output signal will be OFF. Otherwise, the output signal will be ON. | The '''NAND gate''' accepts two inputs. It is generally equivalent to an AND gate immediately followed by an inverter. If both input signals are ON, the output signal will be OFF. Otherwise, the output signal will be ON. | ||
The point of including a NAND gate when an inverter can simply be placed after a regular AND gate, aside from speed and compactness, may be to demonstrate [http://en.wikipedia.org/wiki/NAND_logic NAND logic]: all other logic gates can be constructed with only combinations of NAND gates. Its inclusion over a NOR gate would be arbitrary, as similar [http://en.wikipedia.org/wiki/NOR_logic NOR logic] exists. | |||
{| class="wikitable" | {| class="wikitable" | ||