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== Logic Gates == | |||
{{Infobox Game Tile | |||
|name = Logic gate | |||
|image = [[Image:NOTgate.png]] [[Image:ANDgate.png]] [[Image:ORgate.png]] [[Image:NANDgate.png]] [[Image:XORgate.png]] | |||
|cc1 = | |||
|cc2 = Yes | |||
|cc1index = | |||
|multidirectional = Yes | |||
|moves = No | |||
}} | |||
'''Logic gates''' perform a logical operation on one or two wire inputs and produce a single output. They consist of the inverter, AND gate, OR gate, NAND gate, and XOR gate. There also exist NOR and XNOR logic gates, but these are not present in Chip's Challenge 2. | |||
=== Inverter === | |||
[[File:NOTgate.png|left]] | |||
The '''inverter''', also called the '''NOT gate''', accepts a single input and inverts the signal. If its input signal is ON, the output signal will be OFF. If its input signal is OFF, the output signal will be ON. | |||
{| class="wikitable" | |||
|- style="background:#def; text-align:center;" | |||
|'''INPUT''' || '''OUTPUT''' | |||
|- style="background:#def; text-align:center;" | |||
| A || NOT A | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 0 | |||
|} | |||
=== AND gate === | |||
[[File:ANDgate.png|left]] | |||
The '''AND gate''' accepts two inputs. If both inputs signals are ON, the output signal will be ON. Otherwise, the output signal will be OFF. | |||
{| class="wikitable" | |||
|- style="background:#def; text-align:center;" | |||
|colspan=2|'''INPUT''' || '''OUTPUT''' | |||
|- style="background:#def; text-align:center;" | |||
| A || B || A AND B | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 0 || 0 | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 1 || 0 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 0 || 0 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 1 || 1 | |||
|} | |||
=== OR gate === | |||
[[File:ORgate.png|left]] | |||
The '''OR gate''' accepts two inputs. If at least one of the input signals are ON, the output signal will be ON. Otherwise, the output signal will be OFF. | |||
{| class="wikitable" | |||
|- style="background:#def; text-align:center;" | |||
|colspan=2|'''INPUT''' || '''OUTPUT''' | |||
|- style="background:#def; text-align:center;" | |||
| A || B || A OR B | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 0 || 0 | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 1 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 0 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 1 || 1 | |||
|} | |||
=== NAND gate === | |||
[[File:NANDgate.png|left]] | |||
The '''NAND gate''' accepts two inputs. It is equivalent to an AND gate immediately followed by an inverter. If both input signals are ON, the output signal will be OFF. Otherwise, the output signal will be on. | |||
{| class="wikitable" | |||
|- style="background:#def; text-align:center;" | |||
|colspan=2|'''INPUT''' || '''OUTPUT''' | |||
|- style="background:#def; text-align:center;" | |||
| A || B || A NAND B | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 0 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 1 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 0 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 1 || 0 | |||
|} | |||
=== XOR gate === | |||
[[File:XORgate.png|left]] | |||
The '''XOR gate''' gate accepts two inputs and performs an ''exclusive or'' operation. If one or the other of the two input signals is ON, the output signal will be ON. If neither input signals are ON or both input signals are ON, the output signal will be OFF. | |||
{| class="wikitable" | |||
|- style="background:#def; text-align:center;" | |||
|colspan=2|'''INPUT''' || '''OUTPUT''' | |||
|- style="background:#def; text-align:center;" | |||
| A || B || A XOR B | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 0 || 0 | |||
|- style="background:#dfd; text-align:center;" | |||
|0 || 1 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 0 || 1 | |||
|- style="background:#dfd; text-align:center;" | |||
|1 || 1 || 0 | |||
|} | |||